A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of highperformance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12µm technology showing excellent results.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: José Luis Rosselló, Vicens Canals, Sebastiàn A. Bota, Ali Keshavarzi, Jaume Segura
• Keywords: DATE 2005, Hardware, Static Power, Static Power Dissipation, Total Power