Fast performance analysis of bus-based system-on-chip communication architectures

This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework (e.g., simulation of the complete system), or are not accurate enough to drive the design of the communication architecture (e.g., techniques that perform a "static" analysis of the system performance). The proposed system-level performance analysis technique consists of (i) initial co-simulation performed after HW/SW partitioning and mapping, with the communication between components modeled in an abstract manner (e.g., as events or data transfers), (ii) extraction of abstracted symbolic traces, represented as a Bus and Synchronization Event (BSE) Graph, that captures the activity of the various system components and the...

• Type: Conference
• Year: 1999
• Where: ICCAD
• Authors: Kanishka Lahiri, Anand Raghunathan, Sujit Dey
• Keywords: Communication Architecture, Hardware, ICCAD 1999, Performance Analysis, System-level Performance Analysis