Fast Run-Time Power Monitoring Methodology for Embedded Systems

Traditional simulation-based energy estimation is not practical because the simulation time has increased from minutes and hours and weeks. Therefore, simulation assisted by special hardware, such as FPGA, is the best solution for speeding up the simulation of large design. In this presentation we describe a coordinated measurement approach that combines off-line measured power models with counter-based, per-unit power estimation on FPGA emulation board. We port our CCU32 processor core and CCU DSP5 core into the Altera Excalibur EPXA10 emulation board and write an application running on these cores. The power monitor tool provides live total power measurements to identify the hot spots of a program. Overall, this design demonstrates a power measurement and estimation infrastructure which can provide a basis for future poweraware tool kits development.

• Type: Conference
• Year: 2006
• Where: CSREAESA
• Authors: Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
• Keywords: CSREAESA 2006, CSREAESA 2007, Per-unit Power Estimation, Power Measurement, Simulation-based Energy Estimation