FastRoute 4.0: global router with efficient via minimization

The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by charging a cost for vias in the maze routing cost function. In this paper, we present a global router that addresses the via number optimization problem throughout the entire global routing flow. We introduce the via aware Steiner tree generation, 3-bend routing and layer assignment with careful ordering to reduce via count. We integrate these three techniques into FastRoute 3.0 and achieve significant reduction in both via count and runtime.

• Type: Conference
• Year: 2009
• Where: ASPDAC
• Authors: Yue Xu, Yanheng Zhang, Chris Chu
• Keywords: ASPDAC 2009, Global Router, Global Routing, Global Routing Stage, Hardware