Fault Coverage Estimation for Early Stage of VLSI Design

This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with three parameters, which include the fault coverage upper bound, UB, the fault coverage lower bound, LB, and the rate of fault coverage change, . The fault coverages using three di erent testing scenarios, which are no DFT, scan, iddq testing, are predicted using circuit design information, such as gate count, IO count, and FF count. These parameters are often readily available at the esrly stage of VLSI design. Finally, the composite fault coverage is estimated by combining di erent fault coverages. Experimental

• Type: Conference
• Year: 1999
• Where: GLVLSI
• Authors: Von-Kyoung Kim, Tom Chen, Mick Tegethoff
• Keywords: Fault Coverage Estimation, Fault Coverage Model, Fault Coverages, GLVLSI 1999, VLSI