A Fault Tolerant Clock Synchronization Algorithm for Systems with Low-Precision Oscillators

In this paper we present a new fault tolerant clock synchronization algorithm called the Fault Tolerant Daisy Chain algorithm. It is intended for internal clock synchronization of systems using a broadcast bus with Time Division Multiple Access (TDMA) communication, or other systems where clock readings are broadcast at regular intervals. The algorithm allows synchronization after each clock reading and is therefore more tolerant to oscillators with large drift rates. Clock hardware is simplified since it is not necessary to store the collected clock readings until the next synchronization, nor is it necessary to schedule synchronization events. The algorithm is therefore suitable for cost sensitive application areas such as the automotive industry. Theoretical bounds on clock skew are derived for an arbitrary number of non-Byzantine and Byzantine faults and compared with three different convergence synchronization algorithms. A simulation study where transient errors were injected on...

• Type: Conference
• Year: 1999
• Where: EDCC
• Authors: Henrik Lönn
• Keywords: Applied Computing, Clock, EDCC 1999, Synchronization, Synchronization Algorithm