Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors

Abstract: Polynomial computations over fixed-size bitvectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositions of the polynomial into smaller/simpler units. Symbolic computer algebra algorithms and tools have been used for this purpose. However, fixed-size (m) bit-vector arithmetic is polynomial algebra over the finite integer ring Z2m , which is a non-unique factorization domain (non-UFD). While non-UFDs provide an extra freedom to search for decompositions, they complicate polynomial manipulation as traditional division-based algorithms are inapplicable. This paper presents new mathematical concepts for polynomial decomposition over Z2m , for RTL synthesis over fixedsize m-bit vectors. Given a polynomial, we identify a specific set of linear expressions and compute the Gr

• Type: Conference
• Year: 2007
• Where: ICCAD
• Authors: Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon Meredith, Florian Enescu
• Keywords: Hardware, ICCAD 2007, Polynomial, Polynomial Computations, RTL Synthesis