FinFETs for nanoscale CMOS digital integrated circuits

Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the FinFET will likely be necessary to meet transistor performance requirements in the sub-20nm gate length regime. This paper presents an overview of FinFET technology and describes how it can be used to improve the performance, standby power consumption, and variability in nanoscale-CMOS digital ICs. Keywords MOSFET, thin-body transistor, CMOS, SRAM, digital IC

• Type: Conference
• Year: 2005
• Where: ICCAD
• Authors: Tsu-Jae King
• Keywords: Hardware, ICCAD 2005, Non-classical Transistor Structures, Sub-45nm Cmos Technologies, Transistor Performance Requirements