ICCAD 2005 - PDF Preprint Papers

ICCAD 2005 International Conference on Computer-Aided Design

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ICCAD
2005
IEEE

200views Hardware» more ICCAD 2005»

CDMA/FDMA-interconnects for future ULSI communications

14 years 9 months ago

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Future inter- and intra-ULSI interconnect systems demand extremely high data rates as well as bi-directional multi-I/O concurrent service, re-configurable computing/processing arc...

M. Frank Chang

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Id	Views	Title	Status

1	200	CDMA/FDMA-interconnects for future ULSI communications	claim
2	199	FinFETs for nanoscale CMOS digital integrated circuits	claim
3	176	Statistical gate sizing for timing yield optimization	claim
4	168	Statistical timing analysis driven post-silicon-tunable clock-tree synthesis	claim
5	160	Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra	claim
6	151	Architecture and details of a high quality, large-scale analytical placer
7	147	NoCEE: energy macro-model extraction methodology for network on chip routers	claim
8	145	Noise margin analysis for dynamic logic circuits	claim
9	144	An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications	claim
10	141	Architecture and compilation for data bandwidth improvement in configurable embedded processors	claim
11	140	Embedded tutorial: formal equivalence checking between system-level models and RTL	claim
12	134	Fast thermal simulation for architecture level dynamic thermal management	claim
13	133	Gate sizing using incremental parameterized statistical timing analysis	claim
14	133	Memory access optimization of dynamic binary translation for reconfigurable architectures	claim
15	132	Serial-link bus: a low-power on-chip bus architecture	claim
16	132	Battery optimization vs energy optimization: which to choose and when?	claim
17	131	Code restructuring for improving cache performance of MPSoCs	claim
18	130	A cache-defect-aware code placement algorithm for improving the performance of processors	claim
19	128	Reducing structural bias in technology mapping	claim
20	127	Flip-flop insertion with shifted-phase clocks for FPGA power reduction	claim
21	127	Hardware synthesis from guarded atomic actions with performance specifications	claim
22	125	Robust mixed-size placement under tight white-space constraints	claim
23	123	Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation	claim
24	122	Intrinsic shortest path length: a new, accurate a priori wirelength estimator
25	121	Transition-by-transition FSM traversal for reachability analysis in bounded model checking	claim
26	120	Practical techniques to reduce skew and its variations in buffered clock networks	claim
27	118	Thermal via planning for 3-D ICs	claim
28	117	IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs	claim
29	114	Statistical timing analysis with two-sided constraints	claim
30	114	Double-gate SOI devices for low-power and high-performance applications	claim
31	113	Synthesis methodology for built-in at-speed testing	claim
32	112	Global signaling over lossy transmission lines	claim
33	110	Computational geometry based placement migration	claim
34	110	A hybrid linear equation solver and its application in quadratic placement	claim
35	110	Performance analysis of carbon nanotube interconnects for VLSI applications	claim
36	108	A routing algorithm for flip-chip design	claim
37	107	Projection-based performance modeling for inter/intra-die variations	claim
38	106	New decompilation techniques for binary-level co-processor generation	claim
39	106	FPGA device and architecture evaluation considering process variations	claim
40	106	Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration	claim
41	105	Response shaper: a novel technique to enhance unknown tolerance for output response compaction	claim
42	105	Weighted control scheduling	claim
43	104	Design of DNA origami	claim
44	101	Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations	claim
45	101	FastSies: a fast stochastic integral equation solver for modeling the rough surface effect	claim
46	100	Performance-centering optimization for system-level analog design exploration	claim
47	98	Statistical based link insertion for robust clock network design	claim
48	98	Clustering for processing rate optimization	claim
49	98	An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems	claim
50	97	DiCER: distributed and cost-effective redundancy for variation tolerance	claim
51	96	A more reliable reduction algorithm for behavioral model extraction	claim
52	95	TACO: temperature aware clock-tree optimization	claim
53	95	Application-specific network-on-chip architecture customization via long-range link insertion	claim
54	94	Post-placement voltage island generation under performance requirement	claim
55	93	Eliminating wire crossings for molecular quantum-dot cellular automata implementation	claim
56	90	Scalable compositional minimization via static analysis	claim
57	90	Thermal simulation techniques for nanoscale transistors	claim
58	87	Parameterized model order reduction of nonlinear dynamical systems	claim
59	87	Statistical technology mapping for parametric yield	claim
60	86	Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems	claim
61	84	Total power-optimal pipelining and parallel processing under process variations in nanometer technology	claim
62	83	Post-placement rewiring and rebuffering by exhaustive search for functional symmetries	claim
63	83	Computer-aided design for DNA self-assembly: process and applications	claim
64	83	System software techniques for low-power operation in wireless sensor networks	claim
65	81	Kauffman networks: analysis and applications	claim
66	79	The impact of the nanoscale on computing systems	claim
67	79	Storage assignment during high-level synthesis for configurable architectures	claim
68	79	Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillators	claim
69	79	Discrete Vt assignment and gate sizing using a self-snapping continuous formulation	claim
70	76	A unified framework for statistical timing analysis with coupling and multiple input switching	claim
71	73	The feasibility of on-chip interconnection using antennas	claim
72	71	Simulation-based bug trace minimization with BMC-based refinement	claim
73	70	Physics-based compact modeling for nonclassical CMOS	claim

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