FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths

Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing the hardware to suit an application. A central problem is creating compilers that are capable of dealing with the heterogeneous and non-uniform hardware created by the customization process. The processor datapath provides an effective area to customize, but specialized datapaths often have non-uniform connectivity between the function units, making the effective latency of a function unit dependent on the consuming operation. Traditional instruction schedulers break down in this environment due to their locally greedy nature of binding the best choice for a single operation even though that choice may be poor due to a lack of communication paths. To effectively schedule with non-uniform connectivity, we propose a foresighted latencyaware scheduling heuristic (FLASH) that performs lookahead across future sche...

• Type: Conference
• Year: 2004
• Where: CGO
• Authors: Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke
• Keywords: CGO 2004, Function Unit, Instruction Set Processors, Non-uniform Connectivity, Software Engineering