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    CGO
    2004
    IEEE
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    FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
    13 years 10 months ago
    FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
    Download  cccp.eecs.umich.edu
    Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
    Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
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