Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors

Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of a local register file and a subset of the functional units, while the data cache remains centralized. However, as technology evolves, the latency of such a centralized cache will increase leading to an important performance impact. In this paper we propose to include flexible low-latency buffers in each cluster in order to reduce the performance impact of higher cache latencies. The reduced number of entries in each buffer permits the design of flexible ways to map data from L1 to these buffers. The proposed L0 buffers are managed by the compiler, which is responsible to decide which memory instructions make use of them. Effective instruction scheduling techniques are proposed to generate code that exploits these buffers. Results for the Mediabench benchmark suite sho...

• Type: Conference
• Year: 2003
• Where: MICRO
• Authors: Enric Gibert, F. Jesús Sánchez, Antonio González
• Keywords: Data Cache, Hardware, L1 Data Cache, MICRO 2003, flexible Low-latency Buffers