MICRO 2003 - PDF Preprint Papers

MICRO 2003 IEEE/ACM International Symposium on Microarchitecture

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MICRO
2003
IEEE

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LLVA: A Low-level Virtual Instruction Set Architecture

14 years 5 months ago

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A virtual instruction set architecture (V-ISA) implemented via a processor-speciﬁc software translation layer can provide great ﬂexibility to processor designers. Recent examp...

Vikram S. Adve, Chris Lattner, Michael Brukman, An...

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Id	Views	Title	Status

1	258	LLVA: A Low-level Virtual Instruction Set Architecture	claim
2	166	Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation	claim
3	161	Design and Implementation of High-Performance Memory Systems for Future Packet Buffers	claim
4	155	Comparing Program Phase Detection Techniques	claim
5	152	A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor	claim
6	148	Fast Secure Processor for Inhibiting Software Piracy and Tampering	claim
7	147	Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors	claim
8	143	VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power	claim
9	142	Hardware Support for Control Transfers in Code Caches	claim
10	135	Generational Cache Management of Code Traces in Dynamic Optimization Systems	claim
11	132	Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors	claim
12	128	IPStash: a Power-Efficient Memory Architecture for IP-lookup	claim
13	125	Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data	claim
14	125	WaveScalar	claim
15	124	Optimum Power/Performance Pipeline Depth	claim
16	121	Exploiting Value Locality in Physical Register Files	claim
17	116	Universal Mechanisms for Data-Parallel Architectures	claim
18	109	TLC: Transmission Line Caches	claim
19	108	Reducing Design Complexity of the Load/Store Queue	claim
20	106	Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction	claim
21	106	Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches	claim
22	101	Macro-op Scheduling: Relaxing Scheduling Loop Constraints	claim
23	100	The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System	claim
24	99	Power-driven Design of Router Microarchitectures in On-chip Networks	claim
25	96	Using Interaction Costs for Microarchitectural Bottleneck Analysis	claim
26	96	Scalable Hardware Memory Disambiguation for High ILP Processors	claim
27	95	Processor Acceleration Through Automated Instruction Set Customization	claim
28	88	Instruction Replication for Clustered Microarchitectures	claim
29	70	Fast Path-Based Neural Branch Prediction	claim

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