Floorplan-based FPGA interconnect power estimation in DSP circuits

A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to interconnections between modules and depends only on their mutual distance and shape. The power model has been characterized and verified with on-board power measurements, instead of using low-level estimation tools which often lack the required accuracy (observed errors go up to 350%). The results show that most of the errors of the presented power model lie within 20% of the physical measurements. This is an excellent result considering that in [2] it is shown that there is already a 20% variation in net capacitance due to the different routing solutions given by router for the same placement. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles— Gate arrays General Terms Algorithms, Design Keywords FPGA, low power, interconnects, power estimation

• Type: Conference
• Year: 2009
• Where: SLIP
• Authors: Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
• Keywords: Computer Networks, On-board Power Measurements, Power Model, Presented Power Model, SLIP 2009