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2002

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

13 years 11 months ago
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The proposed reseeding technique is generic and can be applied to TPGs based on both Linear Feedback Shift Registers (LFSRs) and accumulators. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and allows to well exploiting the trade-off between hardware overhead and test length. Using experimental results we show that the proposed method compares favorably to the other already known techniques with respect to test length and the hardware implementation cost.
Emmanouil Kalligeros, Xrysovalantis Kavousianos, D
Added 18 Dec 2010
Updated 18 Dec 2010
Type Journal
Year 2002
Where ET
Authors Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
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