Sciweavers

ICDE
2010
IEEE

FPGA Acceleration for the Frequent Item Problem

15 years 1 days ago
FPGA Acceleration for the Frequent Item Problem
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show how to employ FPGAs to provide an efficient and high-performance solution for the frequent item problem. We discuss three design alternatives, each one of them exploiting different FPGA features, and we provide an exhaustive evaluation of their performance characteristics. The first design is a one-to-one mapping of the Space-Saving algorithm (shown to be the best approach in software [1]), built on special features of FPGAs: content-addressable memory and dual-ported BRAM. The two other implementations exploit the flexibility of digital circuits to implement parallel lookups and pipelining strategies, resulting in significant improvements in performance. On low-cost FPGA hardware, the fastest of our designs can process 80 million items per second--three times as much as the best known result. Moreover, and ...
Gustavo Alonso, Jens Teubner, René Mül
Added 20 Dec 2009
Updated 03 Jan 2010
Type Conference
Year 2010
Where ICDE
Authors Gustavo Alonso, Jens Teubner, René Müller
Comments (0)