FPGA Implementation of a Maze Routing Accelerator

This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-reroute. A 16 X 16 single-layer and 4 X 4 multi-layer router that can handle 2-16 layers have been implemented in a low-end Xilinx XC2S300E FPGA. Larger arrays are currently under construction.

• Type: Conference
• Year: 2003
• Where: FPL
• Authors: John A. Nestor
• Keywords: FPL 2003, Maze Routing Accelerator, Preferential Routing, Xilinx XC2S300E FPGA