FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks

This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. We demonstrate that recent reconfigurable devices offer excellent opportunities to implement a masked DES. In particular, we use the large embedded memories available in the Xilinx Virtex-II pro FPGAs to store precomputed and masked substitution tables. Compared to an unprotected DES design, our proposal only requires 45% more logic resources and 128 Kbit of memory and yields a throughput of about 1 Gbit/sec.

• Type: Conference
• Year: 2006
• Where: FPL
• Authors: François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater
• Keywords: FPL 2006, Hardware, Power Analysis Attacks, Smart Card Implementations, Unprotected Des Design