FPGA Interconnect Delay Fault Testing

The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple interconnect delay faults, multiple bridging faults, or both. An adjustable maximum sensitivity to resistive open defects of several kilo-ohms is achieved. A bridging fault that causes a signal transition to occur on at least one of the bridged interconnects is detectable. Finally, fast and simple fault location is presented.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Erik Chmelar
• Keywords: Adjustable Maximum Sensitivity, Hardware, Interconnect Delay Faults, ITC 2003, Multiple Bridging Faults