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40

FPL
2005
Springer

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An FPGA Network Architecture for Accelerating 3DES - CBC

14 years 4 months ago

An FPGA Network Architecture for Accelerating 3DES - CBC

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This paper presents a DES/3DES core that will support Cipher Block Chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virtex II 1000-4. The core will achieve up to 200Mbit/s of encryption or decryption. Also presented is a network architecture that will allow these CBC capable 3DES cores to perform their processing in parallel.

Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann

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CBC Capable 3DES | Cipher Block Chaining | FPL 2005 | Xilinx Virtex II |

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Added	27 Jun 2010
Updated	27 Jun 2010
Type	Conference
Year	2005
Where	FPL
Authors	Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann

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