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FPL
2005
Springer
130views Hardware» more  FPL 2005»
14 years 6 months ago
Communication Synthesis in a multiprocessor environment
At Leiden University, we are developing a design methodology that allows for fast mapping of nested-loop applications (e.g. DSP, Imaging, or MultiMedia) written in a subset of Matl...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...
FPL
2005
Springer
113views Hardware» more  FPL 2005»
14 years 6 months ago
Ziggurat-based Hardware Gaussian Random Number Generator
An architecture and implementation of a high performance Gaussian random number generator (GRNG) is described. The GRNG uses the Ziggurat algorithm which divides the area under th...
Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee,...
FPL
2005
Springer
137views Hardware» more  FPL 2005»
14 years 6 months ago
Bitwise Optimised CAM for Network Intrusion Detection Systems
String pattern matching is a computationally expensive task, and when implemented in hardware, it can consume a large amount of resources for processing and storage. This paper pr...
Sherif Yusuf, Wayne Luk
FPL
2005
Springer
73views Hardware» more  FPL 2005»
14 years 6 months ago
Energy-Efficient NoC for Best-Effort Communication
A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-onChip (MPSoC) architectures. In an earlier paper we proposed a energ...
Pascal T. Wolkotte, Gerard J. M. Smit, Jens E. Bec...
FPL
2005
Springer
172views Hardware» more  FPL 2005»
14 years 6 months ago
An FPGA Network Architecture for Accelerating 3DES - CBC
This paper presents a DES/3DES core that will support Cipher Block Chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virte...
Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann
FPL
2005
Springer
139views Hardware» more  FPL 2005»
14 years 6 months ago
Mullet - A Parallel Multiplier Generator
A module generator called Mullet for producing near-optimal parallel multipliers in a technology independent manner is presented. Using this tool, a large number of candidate desi...
Kuen Hung Tsoi, Philip Heng Wai Leong
FPL
2005
Springer
115views Hardware» more  FPL 2005»
14 years 6 months ago
Statistical Power Estimation for FPGA
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...
FPL
2005
Springer
111views Hardware» more  FPL 2005»
14 years 6 months ago
Mutable Codesign for Embedded Protocol Processing
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
Todd S. Sproull, Gordon J. Brebner, Christopher E....
FPL
2005
Springer
113views Hardware» more  FPL 2005»
14 years 6 months ago
A Reconfigurable Perfect-Hashing Scheme for Packet Inspection
In this paper, we consider scanning and analyzing packets in order to detect hazardous contents using pattern matching. We introduce a hardware perfect-hashing technique to access...
Ioannis Sourdis, Dionisios N. Pnevmatikatos, Steph...
FPL
2005
Springer
138views Hardware» more  FPL 2005»
14 years 6 months ago
Snort Offloader: A Reconfigurable Hardware NIDS Filter
Software-based Network Intrusion Detection Systems (NIDS) often fail to keep up with high-speed network links. In this paper an FPGA-based pre-filter is presented that reduces th...
Haoyu Song, Todd S. Sproull, Michael Attig, John W...