FPGAs for High Accuracy Clock Synchronization over Ethernet Networks

This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The network interface node on one hand provides all necessary hardware support to be flexibly used in a broad range of applications. The switch add-on on the other hand accounts for the packet delay uncertainties of Ethernet switches and is crucial for high accuracy clock synchronization.

• Type: Conference
• Year: 2003
• Where: FPL
• Authors: Roland Höller
• Keywords: Accuracy Clock Synchronization, FPL 2003, Network Interface Node, Packet Delay Uncertainties