A Framework for Parallelizing Load/Stores on Embedded Processors

Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve code density and/or performance. In order to effectively utilize the parallel load/store instructions, the compiler must partition the memory resident values into X or Y bank. This paper gives a post-register allocation solution to merge the generated load/store instructions into their parallel counter-parts. Simultaneously, our framework performs allocation of values to X or Y memory banks. We first remove as many load/stores and registerregister moves through an excellent iterated coalescing based register allocator by Appel and George[14]. We then attempt to maximally parallelize the generated load/stores using a multi-pass approach with minimal growth in terms of memory requirements. The first phase of our approach attempts the merger of load stores without replication of values in memory. We model this pro...

• Type: Conference
• Year: 2002
• Where: IEEEPACT
• Authors: Xiaotong Zhuang, Santosh Pande, John S. Greenland Jr.
• Keywords: Distributed And Parallel Computing, IEEEPACT 2002, Load/store Instruction, Memory Banks, Parallel Load/store Instructions