Functional Validation of Programmable Architectures

Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. Traditional validation techniques employ t reference models depending on the abstraction level and verification task (e.g., functional simulation or property checking), resulting in potential inconsistencies between multiple reference models. This paper presents a validation methodology that uses an Architecture Description Language (ADL) based specification as a golden reference model for validation of programmable architectures, and generation of executable models such as simulators and hardware prototypes. We present a validation framework that uses the generated hardware as a reference model to verify the hand-written implementation using a combination of symbolic simulation and equivalence checking. We als...

• Type: Conference
• Year: 2004
• Where: DSD
• Authors: Prabhat Mishra, Nikil D. Dutt
• Keywords: DSD 2004, Golden Reference Model, Hardware, Programmable Architectures, Reference Model