Future Performance Challenges in Nanometer Design

We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power scaling trends lead to major packaging problems. To alleviate these concerns, thermal monitoring and feedback mechanisms can limit worst-case dissipation and reduce costs. Furthermore, a flexible multi-Vdd + multi-Vth + re-sizing approach is advocated to leverage the inherent properties of ultrasmall MOSFETs and limit both dynamic and static power. Alternative global signaling strategies such as differential and low-swing drivers are recommended in order to curb the power requirements of crosschip communication. Finally, potential power delivery challenges are addressed with respect to ITRS packaging predictions.

• Type: Conference
• Year: 2001
• Where: DAC
• Authors: Dennis Sylvester, Himanshu Kaul
• Keywords: DAC 2001, Design Automation, ITRS Packaging Predictions, Power Delivery Challenges, Power Scaling Trends