DAC 2001 - PDF Preprint Papers

DAC 2001 Design Automation Conference

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DAC
2001
ACM

250views Computer Architecture» more DAC 2001»

JouleTrack - A Web Based Tool for Software Energy Profiling

15 years 12 days ago

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A software energy estimation methodology is presented that avoids explicit characterization of instruction energy consumption and predicts energy consumption to within 3% accuracy...

Amit Sinha, Anantha Chandrakasan

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Id	Views	Title	Status

1	250	JouleTrack - A Web Based Tool for Software Energy Profiling	claim
2	211	A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs	claim
3	209	Route Packets, Not Wires: On-Chip Interconnection Networks	claim
4	198	Latency-Driven Design of Multi-Purpose Systems-On-Chip	claim
5	181	Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors	claim
6	176	Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems	claim
7	175	Chaff: Engineering an Efficient SAT Solver	claim
8	172	Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation	claim
9	163	Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines	claim
10	157	Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers	claim
11	156	Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects	claim
12	155	A Framework for Object Oriented Hardware Specification, Verification, and Synthesis	claim
13	153	Coupling-Driven Bus Design for Low-Power Application-Specific Systems	claim
14	151	On-Chip Communication Architecture for OC-768 Network Processors	claim
15	148	Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems	claim
16	147	A True Single-Phase 8-bit Adiabatic Multiplier	claim
17	147	Circuit-based Boolean Reasoning	claim
18	146	System-Level Power/Performance Analysis for Embedded Systems Design	claim
19	146	A Quick Safari Through the Reconfiguration Jungle	claim
20	145	Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems	claim
21	143	An Advanced Timing Characterization Method Using Mode Dependency	claim
22	142	An Algorithm for Bi-Decomposition of Logic Functions	claim
23	142	Using Texture Mapping with Mipmapping to Render a VLSI Layout	claim
24	138	Publicly Detectable Techniques for the Protection of Virtual Components	claim
25	138	Hardware/Software Instruction Set Configurability for System-on-Chip Processors	claim
26	138	Watermarking Graph Partitioning Solutions	claim
27	137	Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design	claim
28	137	Dynamic Voltage Scaling and Power Management for Portable Systems	claim
29	135	Hypermedia-Aided Design	claim
30	135	Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip	claim
31	135	Fast Statistical Timing Analysis By Probabilistic Event Propagation	claim
32	134	MicroNetwork-Based Integration for SOCs	claim
33	133	Creating and Exploiting Flexibility in Steiner Trees	claim
34	133	Speculation Techniques for High Level Synthesis of Control Intensive Designs	claim
35	132	High-Quality Operation Binding for Clustered VLIW Datapaths	claim
36	131	Address Code Generation for Digital Signal Processors	claim
37	130	Automated Pipeline Design	claim
38	129	Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications	claim
39	128	Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks	claim
40	128	Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores	claim
41	127	Scalable Hybrid Verification of Complex Microprocessors	claim
42	127	Transformations for the Synthesis and Optimization of Asynchronous Distributed Control	claim
43	126	LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs	claim
44	125	Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods	claim
45	125	A New Structural Pattern Matching Algorithm for Technology Mapping	claim
46	124	Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs	claim
47	124	Future Performance Challenges in Nanometer Design	claim
48	122	Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping	claim
49	121	Factoring and Recognition of Read-Once Functions using Cographs and Normality	claim
50	121	Static Scheduling of Multiple Asynchronous Domains For Functional Verification	claim
51	121	MetaCores: Design and Optimization Techniques	claim
52	121	An Approach to Incremental Design of Distributed Embedded Systems	claim
53	118	Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect	claim
54	115	A Practical Methodology for Early Buffer and Wire Resource Allocation	claim
55	114	Re-Configurable Computing in Wireless	claim
56	112	Test Volume and Application Time Reduction Through Scan Chain Concealment	claim
57	112	Watermarking of SAT using Combinatorial Isolation Lemmas	claim
58	112	Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk	claim
59	108	Semi-Formal Test Generation with Genevieve	claim
60	108	Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors	claim
61	107	A New Gate Delay Model for Simultaneous Switching and Its Applications	claim
62	107	Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service	claim
63	105	Clustered VLIW Architectures with Predicated Switching	claim
64	105	Using Symbolic Algebra in Algorithmic Level DSP Synthesis	claim
65	105	Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling	claim
66	105	Improved Cut Sequences for Partitioning Based Placement	claim
67	101	Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint	claim
68	100	An Interconnect Energy Model Considering Coupling Effects	claim
69	97	A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC	claim
70	97	High-level Software Energy Macro-modeling	claim
71	90	SoC Integration of Reusable Baseband Bluetooth IP	claim

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