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43

ASYNC
2007
IEEE

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Gate-level modelling and verification of asynchronous circuits using CSPM and FDR

14 years 5 months ago

Gate-level modelling and verification of asynchronous circuits using CSPM and FDR

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Mark B. Josephs

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Added	02 Jun 2010
Updated	02 Jun 2010
Type	Conference
Year	2007
Where	ASYNC
Authors	Mark B. Josephs

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