Generating Checking Sequences for Partial Reduced Finite State Machines

The problem of generating checking sequences for FSMs with distinguishing sequence has been attracting interest of researchers for several decades. In this paper, a solution is proposed for partial reduced FSMs with distinguishing sets, and either with or without reset feature. Sufficient conditions for a sequence to be a checking sequence for such FSMs are formulated. Based on these conditions, a method to generate checking sequence is elaborated. The results of an experimental comparison indicate that the proposed method produces shorter checking sequences than existing methods in most cases. The impact of using the reset feature on the length of checking sequence is also experimentally evaluated.

• Type: Conference
• Year: 2008
• Where: PTS
• Authors: Adenilso da Silva Simão, Alexandre Petrenko
• Keywords: Checking Sequence, Hardware, Partial Reduced Fsms, PTS 2008, Reset Feature