Generation of Interpretive and Compiled Instruction Set Simulators

Abstract Due to the large variety of di erent embedded processor types, retargetable software development tools, such as compilers and simulators, have received attention recently. Retargetability allows to handle di erent target processors with a single tool. In this paper, we present a system for automatic generation of instruction set simulators for a class of embedded processors. Retargetability is achieved by automatic generation of simulators from processor descriptions, given as behavioral or RT-level HDL models. The presented system is capable of bit-true simulation for arbitrary processor word lengths, and it generates both interpretive or compiled simulators. Experimental results for di erent processors indicate comparatively high simulation speed.

• Type: Conference
• Year: 1999
• Where: ASPDAC
• Authors: Rainer Leupers, Johann Elste, Birger Landwehr
• Keywords: ASPDAC 1999, Automatic Generation, Embedded Processors, Erent Embedded Processor, Hardware