ASPDAC 1999 - PDF Preprint Papers

ASPDAC 1999 Asia and South Pacific Design Automation Conference

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ASPDAC
1999
ACM

173views Hardware» more ASPDAC 1999»

Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs

14 years 4 months ago

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Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Go...

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Id	Views	Title	Status

1	173	Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs	claim
2	168	An Integrated Battery-Hardware Model for Portable Electronics	claim
3	157	A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph Optimization	claim
4	151	Benchmark Circuits Improve the Quality of a Standard Cell Library	claim
5	149	The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance	claim
6	144	Model Order Reduction of Large Circuits Using Balanced Truncation	claim
7	143	Crosstalk Reduction by Transistor Sizing	claim
8	137	A Performance-Driven I/O Pin Routing Algorithm	claim
9	135	A High Speed and Low Power Phase-Frequency Detector and Charge - pump	claim
10	132	Faster and Better Spectral Algorithms for Multi-Way Partitioning	claim
11	123	Estimation of Peak Current through CMOS VLSI Circuit Supply Lines	claim
12	122	A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning	claim
13	117	Analysing Forced Oscillators with Multiple Time Scales	claim
14	116	An Automatic Router for the Pin Grid Array Package	claim
15	113	An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures	claim
16	112	Relaxed Simulated Tempering for VLSI Floorplan Designs	claim
17	107	New Multilevel and Hierarchical Algorithms for Layout Density Control	claim
18	107	Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment	claim
19	105	Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion	claim
20	101	Fast Boolean Matching Under Permutation Using Representative	claim
21	101	Optimal Evaluation Clocking of Self-Resetting Domino Pipelines	claim
22	100	Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods	claim
23	100	A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition	claim
24	98	Generation of Interpretive and Compiled Instruction Set Simulators	claim
25	98	A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler	claim
26	97	Universal Switched-Current Integrator Blocks for SI Filter Design	claim
27	93	Optimization of Linear Placements for Wirelength Minimization with Free Sites	claim
28	92	Hazard-Free Synthesis and Decomposition of Asynchronous Circuits	claim
29	91	Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair	claim
30	87	VCO Jitter Simulation and Its Comparison With Measurement	claim
31	85	An Efficient Two-Level Partitioning Algorithm for VLSI Circuits	claim
32	84	Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach	claim
33	80	Low Power CMOS Off-Chip Drivers with Slew-rate Difference	claim
34	79	Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors	claim
35	77	Realization of Regular Ternary Logic Functions	claim
36	77	Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming	claim
37	76	Symmetry Detection for Automatic Analog-Layout Recycling	claim
38	72	Motion Estimator LSI for MPEG2 High Level Standard	claim
39	70	A New Pipelined Architecture for Fuzzy Color Correction	claim
40	65	Function Smoothing with Applications to VLSI Layout	claim
41	63	Interconnect Delay Estimation Models for Synthesis and Design Planning	claim
42	60	Timing Optimization of Logic Network Using Gate Duplication	claim
43	56	Waveform Relaxation of Linear Integral-Differential Equations for Circuit Simulation	claim

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