Handling don't-care conditions in high-level synthesis and application for reducing initialized registers

Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle such conditions accurately at the behavior and register transfer levels, which is problematic since the trend is to move toward high-level synthesis. In this work we propose innovative methods to handle such conditions accurately at highlevel designs. In addition, we propose two novel algorithms based on our new methods to minimize the number of registers that need to be initialized at the architecture level, which can reduce the routing resources used by the reset signals and alleviate the routing problem. Our results show that we can identify 53% of the registers that can be uninitialized in a 5-stage pipelined processor within 5 minutes, demonstrating the effectiveness of our approach. Categories and Subject Descriptors B.5.2 [Register-Transfer-Level Implementation]: Design Aids--Optimization General Terms...

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
• Keywords: 5-stage Pipelined Processor, DAC 2009, Design Automation, Logic Synthesis, RTL Symbolic Simulation