A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts

Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Processor). The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software so that the HW cost (gate count) of the designed pipelined ASIP is minimized under given execution cycle and power consumption constraints. A branch-andbound algorithm with proposed lower bound functions is used to solve the presented formalization in the PEAS-I system. The experimental results show that the proposed method is found to be effective and efficient.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi
• Keywords: Computer Architecture, DAC 1996, HW/SW Partitioning Algorithm, Instruction Set Processor, Specific Integrated Processor