DAC 1996 - PDF Preprint Papers

DAC 1996 Design Automation Conference

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DAC
1996
ACM

271views Computer Architecture» more DAC 1996»

Functional Verification Methodology of Chameleon Processor

14 years 3 months ago

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- Functional verification of the new generation microprocessor developed by SGS-THOMSON Microelectronics makes extensive use of advanced technologies. This paper presents a global ...

Françoise Casaubieilh, Anthony McIsaac, Mik...

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Id	Views	Title	Status

1	271	Functional Verification Methodology of Chameleon Processor	claim
2	177	A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis	claim
3	161	Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic	claim
4	157	Computing Parametric Yield Adaptively Using Local Linear Models	claim
5	156	A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts	claim
6	156	Glitch Analysis and Reduction in Register Transfer Level	claim
7	151	Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths	claim
8	150	Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis	claim
9	148	RTL Emulation: The Next Leap in System Verification	claim
10	145	FADIC: Architectural Synthesis applied in IC Design	claim
11	137	Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems	claim
12	136	A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs	claim
13	132	Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time	claim
14	131	Test Point Insertion: Scan Paths through Combinational Logic	claim
15	129	Optimal Clock Skew Scheduling Tolerant to Process Variations	claim
16	128	A New Hybrid Methodology for Power Estimation	claim
17	125	Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design	claim
18	123	Desensitization for Power Reduction in Sequential Circuits	claim
19	122	Efficient Approximation Algorithms for Floorplan Area Minimization	claim
20	122	Integrating Formal Verification Methods with A Conventional Project Design Flow	claim
21	121	Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures	claim
22	121	A Description Language for Design Process Management	claim
23	121	Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications	claim
24	120	Efficient Communication in a Design Environment	claim
25	119	Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design	claim
26	119	VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems	claim
27	115	Bit-Level Analysis of an SRT Divider Circuit	claim
28	114	Design Methodology for Analog High Frequency ICs	claim
29	113	Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems	claim
30	113	POSE: Power Optimization and Synthesis Environment	claim
31	113	Engineering Change in a Non-Deterministic FSM Setting	claim
32	113	Efficient Software Performance Estimation Methods for Hardware/Software Codesign	claim
33	110	A Probability-Based Approach to VLSI Circuit Partitioning	claim
34	109	Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing	claim
35	108	Word Level Model Checking - Avoiding the Pentium FDIV Error	claim
36	108	A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines	claim
37	108	Module Compaction in FPGA-based Regular Datapaths	claim
38	107	Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems	claim
39	106	Delay Minimal Decomposition of Multiplexers in Technology Mapping	claim
40	105	Design Considerations and Tools for Low-voltage Digital System Design	claim
41	104	Partitioning of VLSI Circuits and Systems	claim
42	103	An O(n) Algorithm for Transistor Stacking with Performance Constraints	claim
43	103	Techniques for Verifying Superscalar Microprocessors	claim
44	102	How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together	claim
45	102	Tutorial: Design of a Logic Synthesis System	claim
46	101	Early Power Exploration - A World Wide Web Application	claim
47	101	Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral Transforms	claim
48	100	Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis	claim
49	100	A Register File and Scheduling Model for Application Specific Processor Synthesis	claim
50	100	A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications	claim
51	100	Improving the Efficiency of Power Simulators by Input Vector Compaction	claim
52	99	Compact Vector Generation for Accurate Power Simulation	claim
53	99	A Methodology for Concurrent Fabrication Process/Cell Library Optimization	claim
54	99	Software Development in a Hardware Simulation Environment	claim
55	98	Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures	claim
56	98	Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools	claim
57	98	Analysis of RC Interconnections Under Ramp Input	claim
58	98	An Effective Power Management Scheme for RTL Design Based on Multiple Clocks	claim
59	97	Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance	claim
60	96	Multipole Accelerated Capacitance Calculation for Structures with Multiple Dielectrics with high Permittivity Ratios	claim
61	94	Characterization and Parameterized Random Generation of Digital Circuits	claim
62	94	Application of a Markov Model to the Measurement, Simulation, and Diagnosis of an Iterative Design Process	claim
63	94	Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor	claim
64	94	Opportunities and Obstacles in Low-Power System-Level CAD	claim
65	93	Sizing of Clock Distribution Networks for High Performance CPU Chips	claim
66	93	A Technique for Synthesizing Distributed Burst-mode Circuits	claim
67	93	Issues and Answers in CAD Tool Interoperability	claim
68	92	Concurrent Analysis Techniques for Data Path Timing Optimization	claim
69	88	iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips	claim
70	88	Error Correction Based on Verification Techniques	claim
71	87	Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis	claim
72	87	Implementation of an Efficient Parallel BDD Package	claim
73	86	Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation	claim
74	84	Optimal Clock Period FPGA Technology Mapping for Sequential Circuits	claim
75	83	Power Estimation of Cell-Based CMOS Circuits	claim
76	83	Improved Tool and Data Selection in Task Management	claim
77	81	Post-Layout Optimization for Deep Submicron Design	claim
78	80	Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction	claim
79	79	Electromigration Reliability Enhancement via Bus Activity Distribution	claim
80	78	State Reduction Using Reversible Rules	claim
81	77	A Sparse Image Method for BEM Capacitance Extraction	claim
82	61	Lower Bounds on Test Resources for Scheduled Data Flow Graphs	claim

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