Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors

— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined application-specific instruction set processors, based on hardware/software concurrent engineering approach. An extended taxonomy of inter-instruction dependencies is proposed for the analysis of pipeline hazards. Hardware/software resolution candidates are then associated with these dependencies. Algorithms using the taxonomy and the resolutions are developed to detect and resolve pipeline hazards, and to explore the hardware and software design space. Application benchmarks are used to evaluate the designs and guide the design decision. The power of these tools are demonstrated through the pipeline synthesis of two processors including industrial one. Compared with other approaches, our method achieves higher throughput, and provides a way to explore the hardware/ software tradeoff. Our method can be combine...

• Type: Conference
• Year: 1993
• Where: ICCAD
• Authors: Ing-Jer Huang, Alvin M. Despain
• Keywords: Hardware, Hardware/software Concurrent Engineering, ICCAD 1993, Pipeline Hazards, Pipeline Synthesis