Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration

Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and performance penalty intrinsic in gate-level reconfigurability. To reduce this overhead, coarse-grained reconfigurable arrays (CGRAs) are reconfigurable at the ALU level, but a successful design needs more than computational power—the main bottleneck usually being memory transfers. Just like the integration of hardwired multiplier and memory blocks enabled FPGAs to efficiently implement digital signal processing applications, in this paper we study a customizable architecture template based on heterogeneous processing elements (multipliers, ALU clusters and memories) that provides enough flexibility to realize fast pipelined implementations of various loop kernels on a CGRA.

• Type: Conference
• Year: 2009
• Where: DATE
• Authors: Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
• Keywords: Blocks Enabled Fpgas, Coarse-grained Reconfigurable Arrays, DATE 2009, Hardware, Power—the Main Bottleneck