Hierarchical Error Diagnosis Targeting RTL Circuits

Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to locate design errors. Xlists [1] are shown to be useful to capture the effects of design errors within components of RTL designs. Information from the simulation of Xlists is used to systematically diagnose components in error. Experiments are performed on RTL benchmark circuits using a prototype that we have developed to demonstrate the rapid and accurate location of errors. They also show that diagnosis at the RTL offers a significantly superior alternative to diagnosis at the gate-level both in terms of diagnostic accuracy and computational efficiency.

• Type: Conference
• Year: 2000
• Where: VLSID
• Authors: Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
• Keywords: Design Errors, RTL Circuit Descriptions, Rtl Designs, VLSI, VLSID 2000