High-Level specification and automatic generation of IP interface monitors

A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attack this problem, several researchers have proposed monitor-based methodologies, which offer many benefits. This paper presents a novel, high-level specification style for these monitors, along with a linear-size, linear-time translation algorithm into monitor circuits. The specification style naturally fits the complex, but well-specified interfaces used between IP blocks in systems-on-chip. To demonstrate the advantage of our specification style, we have specified monitors for various versions of the Sonics OCP protocol as well as the AMBA AHB protocol, and have developed a prototype tool that automatically translates specifications into Verilog or VHDL monitor circuits. Categories and Subject Descriptors B.5.2 [Register-Transfer Level Implementation]: Design Aids; B.6.3 [Logic Design]: Design Aids; C.0 [Comp...

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Marcio T. Oliveira, Alan J. Hu
• Keywords: DAC 2002, Design Automation, General--Systems Specification Methodology, Keywords Formal Verification, VHDL Monitor Circuits