High Level Synthesis for Data-Driven Applications

Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware. Presently, logical gates are nearly free and single chips will soon contain billions of gates. However, most current designs are still based on Von Neumann’s architecture because processors are built on this model. Nevertheless, the main current challenge is to be able to design, refine, synthesize and verify new architectures in a minimum time and with a maximum computational performance regardless of the gate count. Data driven architectures enable a high level of parallelism because instead of a single controller managing all the resources (and often a single ALU), tens or hundreds of small controllers can now operate in parallel on local processing units. This paper presents an environment for the high level description, refinement, synthesis and verification of such systems. Our own HDL is present...

• Type: Conference
• Year: 2005
• Where: RSP
• Authors: Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley, Jean-Pierre David
• Keywords: John Von Neumann, Rapid System Prototyping, RSP 2005, Von Neumann, Von Neumann Architecture