A new technique for estimating lower bounds on latency for high level synthesis

In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application of interest. Our proposed technique can be used to compute a tighter earliest scheduling step for nodes (operations) in the Data Flow Graph and thus be used to improve the result quality of any technique requiring the computation of such Ë È values.

• Type: Conference
• Year: 2000
• Where: GLVLSI
• Authors: Helvio P. Peixoto, Margarida F. Jacome
• Keywords: Data Flow Graph, Fast Estimation Technique, GLVLSI 2000, Latency Lower Bounds, VLSI