A High-Performance Hardware Architecture for Spectral Hash Algorithm

—The Spectral Hash algorithm is one of the Round 1 candidates for the SHA-3 family, and is based on spectral arithmetic over a finite field, involving multidimensional discrete Fourier transformations over a finite field, data dependent permutations, Rubic-type rotations, and affine and nonlinear functions. The underlying mathematical structures and operations pose interesting and challenging tasks for computer architects and hardware designers to create fast, efficient, and compact ASIC and FPGA realizations. In this paper, we present an efficient hardware architecture for the full 512bit hash computation using the spectral hash algorithm. We have created a pipelined implementation on a Xilinx Virtex4 XC4VLX200-11 FPGA which yields 100 MHz and occupies

• Type: Conference
• Year: 2009
• Where: ASAP
• Authors: Ray C. C. Cheung, Çetin K. Koç, John D. Villasenor
• Keywords: ASAP 2009, Data Dependent Permutations, Multidimensional Discrete Fourier, Parallel Computing, Spectral Hash Algorithm