ASAP 2009 - PDF Preprint Papers

ASAP 2009 Architectures and Processors Application-Specific Systems

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ASAP-2009 Paper

click to vote

ASAP
2009
IEEE

318views Hardware» more ASAP 2009»

MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA

14 years 2 months ago

Download agora.cs.illinois.edu

Yongchao Liu, Bertil Schmidt, Douglas L. Maskell

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	318	MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA	claim
2	182	NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs	claim
3	159	A High-Performance Hardware Architecture for Spectral Hash Algorithm	claim
4	157	Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing	claim
5	144	Acceleration of Multiresolution Imaging Algorithms: A Comparative Study	claim
6	143	Scalar Processing Overhead on SIMD-Only Architectures	claim
7	142	Parallel Discrete Event Simulation of Molecular Dynamics Through Event-Based Decomposition	claim
8	141	Accelerating a Virtual Ecology Model with FPGAs	claim
9	131	Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system	claim
10	124	Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture	claim
11	120	Design and Implementation of a Radix-4 Complex Division Unit with Prescaling	claim
12	119	A Low Power High Performance Radix-4 Approximate Squaring Circuit	claim
13	115	A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms	claim
14	102	Parallelized Architecture of Multiple Classifiers for Face Detection	claim
15	98	A Power-Scalable Switch-Based Multi-processor FFT	claim
16	95	A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification	claim
17	80	Specialization of the Cell SPE for Media Applications	claim
18	79	Reconfigurable SWP Operator for Multimedia Processing	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers