A High Speed and Low Power Phase-Frequency Detector and Charge - pump

– In this paper, we introduce a high-speed and low power Phase-Frequency Detector (PFD) that is designed using modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop. This PFD has a simpler structure with using only 19 transistors. The operation range of this PFD is

• Type: Conference
• Year: 1999
• Where: ASPDAC
• Authors: Won Hyo Lee, Jun Dong Cho, Sung Dae Lee
• Keywords: ASPDAC 1999, Hardware, Power Phase-frequency Detector, Simpler Structure, True Single-Phase Clock