A high speed low input current low voltage CMOS current comparator

A new high speed low input current comparator is proposed in this paper. Based on a simple negative feedback scheme around the transimpedance stage with an emphasis on a very large loop-gain, the transformed voltage signal is maintained at the lowest swing that results in a speed improvement. On a 0.25um TSMC CMOS process, simulation results demonstrate propagation delays of 3.6ns with ±100nA input current

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: K. Moolpho, Jitkasem Ngarmnil, S. Sitjongsataporn
• Keywords: Input Current Comparator, ISCAS 2003, Negative Feedback Scheme, TSMC CMOS Process