HLS-l: High-level synthesis of high performance latch-based circuits

An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rather than from behavioral description, which can be synthesized to RTL via high-level synthesis (HLS). Sequencing overhead is one of the factors for this performance gap; the choice between latch and flip-flop is not typically taken into account during HLS, even though it affects all the steps of HLS. HLSl is a new design framework that employs high-performance latches during scheduling, allocation, and controller synthesis. Its main feature is a new scheduler that is based on a concept of phase step (as opposed to conventional control step), which allows us scheduling in finer granularity, register allocation that resolves the conflict of latch being read and written at the same time, and controller synthesis that exploits dual-edge triggered storage elements to support phase step based scheduling. In expe...

• Type: Conference
• Year: 2009
• Where: DATE
• Authors: Seungwhun Paik, Insup Shin, Youngsoo Shin
• Keywords: Controller Synthesis, DATE 2009, Hardware, Inherent Performance Gap, Performance Gap