Hydra: An Energy-efficient and Reconfigurable Network Interface

Abstract-- In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces the Hydra: a network interface for the MONTIUM TP, a coarse-grained reconfigurable processor designed for DSP algorithms. We show that the Hydra is energy-efficient and provides the flexibility required to interface processing elements like the MONTIUM TP.

• Type: Conference
• Year: 2006
• Where: ERSA
• Authors: Marcel D. van de Burgwal, Gerard J. M. Smit, Gerard K. Rauwerda, Paul M. Heysters
• Keywords: ERSA 2006, ERSA 2007, Heterogeneous Tiled System-on-chip, Processing Elements, Reconfigurable Network Interface