HPDC
2010
IEEE
13 years 11 months ago
2010
IEEE
Modern scientific collaborations have opened up the opportunity of solving complex problems that involve multidisciplinary expertise and large-scale computational experiments. The...
ERSA
2006
14 years 3 days ago
2006
Abstract-- In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is us...
CVPR
1996
IEEE
14 years 2 months ago
1996
IEEE
Feature indexing techniques are promising for object recognition since they can quickly reduce the set of possible matches for a set of image features. This work exploits another ...
HIPC
2003
Springer
14 years 3 months ago
2003
Springer
High performance computers currently under construction, such as IBM’s Blue Gene/L, consisting of large numbers (64K) of low cost processing elements with relatively small local...
CODES
2003
IEEE
14 years 4 months ago
2003
IEEE
System-on-chip (SoC) designs have the potential to change the way we organize computation. This potential has gone unrealized. Future SoCs will have multiple heterogeneous process...
DATE
2005
IEEE
14 years 4 months ago
2005
IEEE
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
IPPS
2006
IEEE
14 years 4 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
FCCM
2006
IEEE
14 years 4 months ago
2006
IEEE
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...