An ILP formulation for system-level application mapping on network processor architectures

Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. We present an automated system-level design technique for application development on such architectures. The technique incorporates process transformations and block multi-threading aware data mapping to maximize the worst case throughput of the application. We propose integer linear programming formulations for process allocation and data mapping on SMP and block multi-threading based network processors. The paper presents experimental results that evaluate the technique by implementing representative network processing applications on the Intel IXP 2400 architecture. The results demonstrate that our technique is able to generate high-quality mappings of realistic applications on the target architecture within a short time.

• Type: Conference
• Year: 2007
• Where: DATE
• Authors: Christopher Ostler, Karam S. Chatha
• Keywords: DATE 2007, Hardware, Multi-threading Aware Data, Multi-threading Based Network, Network Processors