Implementation of LPM Address Generators on FPGAs

Abstract. We propose the multiple LUT cascade as a means to configure an ninput LPM (Longest Prefix Match) address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n-bit addresses which it matches against k stored prefixes. We implement our

• Type: Conference
• Year: 2006
• Where: ARC
• Authors: Hui Qin, Tsutomu Sasao, Jon T. Butler
• Keywords: Address Generator, ARC 2006, Hardware, LPM Address Generator, Multiple Lut Cascade