Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning

This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. Proposed MC-FPGA uses same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. We also propose an asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts. The proposed architecture is designed using 6-metal 1poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. Keywords-- DPGA, multi-context, asynchronous FPGA.

• Type: Conference
• Year: 2008
• Where: ERSA
• Authors: Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
• Keywords: Context-ID Bits, ERSA 2008, Hardware, Hardware Utilization, Hardware Utilization Ratio