Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit

- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for frame sizes from 576 to 2304 and for five different code rates. H matrix is efficiently generated and stored for a particular frame size and code rate. The encoder is implemented on Reconfigurable Instruction Cell Architecture (RA) which has recently emerged as an ultra low power, high performance, ANSI-C programmable embedded core. Different general and architecture specific optimization techniques are applied to enhance the throughput. With RA, a throughput from 10 to 19 Mbps has been achieved.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Zahid Khan, Tughrul Arslan
• Keywords: ASPDAC 2007, Code Rate, Encoder, Frame Size, Hardware